module par_ser_beh1 (sh_clk, rst, load, par_in, ser_out);
   input       sh_clk;  // shift clock
   input       rst;     // reset signal
   input       load;    // load enable
   input [7:0] par_in;  // parallel input
   output      ser_out; // serial output

   reg [7:0] par_reg;

always @(posedge rst) begin
   par_reg = 8'h00;
end

always  begin
   @(posedge load)
   par_reg = par_in;

   repeat (8) begin
      @(posedge sh_clk)
      par_reg = {1'b0,par_reg[7:1]};
   end
end

assign ser_out = par_reg[0];

endmodule